1. Field of the Invention
This invention relates to control of a single port memory in a computer system. More specifically, the invention relates to controlling flow of information from a single port dynamic random access memory in the computer system to other portions of the computer system such as the display, the CPU, and graphics engine by using parameters to control the duty cycle by which the graphics engine, CPU and display share access to the memory.
2. Description of the Prior Art
Graphics systems for computers include random access graphics display memory (RAM) which is accessed by both the display, the central processing unit (CPU), and the graphics engine (graphics processor). Typically, this memory is dual ported video RAM with one serial port dedicated to the display and one parallel port accessed by the graphics engine and the CPU. However, such video RAM is relatively expensive and it would be more cost effective to use a single port DRAM (dynamic random access memory) memory. The display needs to receive a large amount of data from the memory in order to keep the display refreshed, where the typical bandwidth of data transfer from the memory to the display is 25 to 80 Megabytes per second. The graphics engine (GE) and central processing unit each typically operate at different speeds, at typically one megabyte per second to about 90 megabytes per second. The display is usually given the highest priority for memory access because its screen must be kept continually updated. This is usually accomplished by providing a first in first out (FIFO) memory interposed between the display memory and the display. The FIFO functions as a data "reservoir" and is kept relatively full, so that the display is continually provided with data.
The problem then given the single ported DRAM is making sure that the FIFO is not emptied, and if it is emptied (or nearly so) to ensure that data is immediately provided from display memory and hence to the display; this typically is done by detecting whether the FIFO is full or nearly empty. When the FIFO is full, data is no longer transferred to it from the display memory. When the FIFO is nearly empty, data must be transferred to it immediately. It is difficult to detect exactly when the FIFO is full or empty due to asynchronous clocks of the memory access and display access. To accommodate this uncertainty, a larger size FIFO is needed to avoid FIFO overflow and underflow.
Thus detection of the FIFO being full or empty is relatively difficult and in most systems the FIFO is made relatively large to account for the uncertainty of detection of full and empty. Moreover in the typical prior art system the FIFO pointers pointing to the FIFO read location and write location are compared to determine whether the FIFO is empty or full, and when they are approximately together i.e. within some limit between the read pointer and the write pointer, the FIFO is assumed to be nearly empty. Given the asynchronicity between the display and the graphics engine and CPU and the fact that the display is reading in data at a variety of speeds typically between 25 and 80 MHz, there is further uncertainty which complicates the design and requires a relatively larger FIFO, at additional expense.
Thus there is a need to solve the general problem of data being delivered from the single ported memory at a fixed rate and being distributed between different requesters such as the display, graphics engine and CPU which are asynchronous and typically accepting the data at different rates and also achieves the best possible performance. In other words, there is a need for a relatively simple and reliable scheme to allocate data to the memory requesters.